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NEW QUESTION: 1
View the Exhibit.
Refer to the exhibit above. The Layer 3 switch on the left, DSW1, is the root bridge for all VLANs in the topology. Devices on VLAN 10 use DSW1 as a default gateway. Devices on VLAN 20 use the Layer 3 switch on the right, DSW2, as a default gateway. A device that is operating in VLAN 20 and is connected to ASW3 transmits a packet that is destined beyond Router1.
What path will the packet most likely take through the network?
A. ASW3 > DSW1 > DSW2 > Router1
B. ASW3 > DSW2 > DSW1 > Router1
C. ASW3 > DSW1 > Router1
D. ASW3 > DSW2 > Router1
Answer: A
Explanation:
Explanation/Reference:
Section: Enterprise Network Design Explanation
Explanation:
Most likely, the packet will travel from ASW3 to DSW1, to DSW2, and then to Router1. Because all of the virtual LANs (VLANs) use DSW1 as the root bridge in this scenario, all traffic from the access layer switches, regardless of VLAN, flows first to DSW1. Traffic from VLAN 10 is therefore already optimized because VLAN 10 uses DSW1 as its default gateway. However, VLAN 20 uses DSW2 as its default gateway. Therefore, traffic from VLAN 20 will most likely flow first to DSW1 and then across the PortChannel 1 EtherChannel interface to DSW2 for forwarding.
In this scenario, if you were to configure a separate spanning tree to be established for each VLAN, the location of the root switch could be optimized on a per-VLAN basis. For example, configuring DSW2 as the preferred root bridge for devices that operate on VLAN 20 would cause VLAN 20 traffic from both ASW1 and ASW3 to flow directly to DSW2 for forwarding to Router1. VLAN 10 traffic would remain optimized to flow directly to DSW1 from ASW1, ASW2, or ASW3.
Reference:
CCDA 200-310 Official Cert Guide, Chapter 3, STP Design Considerations, pp. 101-103 Cisco: InterSwitch Link and IEEE 802.1Q Frame Format: Background Theory Cisco: Catalyst 3750X and 3560X Switch Software Configuration Guide, Release 12.2(55)SE: Configuring the Switch Priority of a VLAN
NEW QUESTION: 2
NE A and NE B are adjacent NEs. If B3 and lower-order bit errors occur in the A->B direction and B1, B2, B3, and lower-order bit errors occur in the B->A direction, which of the following performance events are reported by NE A? (Multiple Choice)
A. HPFEBBE
B. MSFEBBE
C. RSBBE
D. RSFEBBE
E. HPBBE
F. MSBBE
Answer: A,C,E,F
NEW QUESTION: 3
情報保護ポリシー（IPP）を構築する場合、記載されているルールが必要であり、適切であり、
A. 機密。
B. 焦点を合わせた。
C. 柔軟。
D. 達成可能。
Answer: D